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VHDLTool is an opensource GNU GPL platform made to improve VHDL developments with continuous code quality management strategy.



It is composed of:

  • A VHDL handbook with standard rules and CNES rules written in XML but converted to pdf.
  • A software bundle tool to convert any VHDL handbooks from XML to PDF (feel free to create you own and get benefit from this conversion from XML to PDF).
  • An eclipse plugin called Zamiacad-Rulechecker based on zamiacad which check the rules into a VHDL project.
  • A scanner for importing rule rule into sonarqube server which will provide nice GUI for checking the rules.

Everything is included inside the ready to try demo  available in the release part of the github:



For any question , request, tutorial or help check the dedicated wiki: